Recently, as the design and manufacture of electronic devices and circuits by conventional, photolithography-based methods has begun to approach physical limits to further decreases in component sizes, alternative methods for manufacturing nanoscale electronic circuits have been developed. Nanowire-crossbar technology is a particularly promising new approach to fabrication of electronic circuits and devices with dimensions significantly less than, and component densities correspondingly greater than, the submicroscale circuits and components that can be currently produced by photolithographic methods.
FIG. 1 illustrates an exemplary nanowire crossbar. The nanowire crossbar in FIG. 1 implements a simple memory device. The nanowire crossbar comprises: (1) a first set of parallel nanowires 102; (2) a bistable bit-storage layer 104; and (3) a second layer of parallel nanowires 106 perpendicular to the first layer of parallel nanowires 102. A single bit of information is stored within each small region of the bit-storage layer 104 at each point of minimal separation, or intersection, between a nanowire of the first layer of nanowires 102 and a nanowire of the second layer of nanowires 106. For example, the small region 108 of the bit-storage layer 104, shown crosshatched in FIG. 1, that overlies nanowire 110 and underlies nanowire 112, forms, along with the portions of nanowires 110 and 112 in contact with the small region, a nanowire junction that serves as a single-bit storage element 114 within the nanoscale memory.
In many nanoscale-memory embodiments, the contents of a single-bit storage element, such as single-bit storage element 114 in FIG. 1, are modified by applying voltage or current signals to one or both of the nanowires that intersect to form the single-bit storage element in order to change a physical state of the bistable bit-storage layer within the nanowire junction, such as the resistivity. In FIG. 1, for example, signals may be applied to one or both of nanowires 110 and 112 to modify single-bit storage element 114, as indicated in FIG. 1 by arrows, such as arrow 116. Generally, no signal, or a different signal, is applied to the remaining nanowires to distinguish the addressed single-bit storage element from all other single-bit storage elements. In many embodiments, signals of relatively large magnitude are applied to carry out WRITE operations, in which a physical state is changed, while relatively smaller magnitude signals are applied to carry out READ operations, in which the physical state is generally not changed, but instead merely determined. In READ operations, a physical state of a single-bit storage element is determined, from the presence, absence, or strength of a signal on one or both of the two nanowires that intersect to form the single-bit storage element, by applying one or more signals to nanowires of the nanowire crossbar. Nanoscale memories implemented by nanowire crossbars can be thought of as two-dimensional arrays of single-bit storage elements, each single-bit storage element separately and uniquely addressable through the two nanowires that intersect to form the single-bit storage element. In certain cases, entire rows, columns, or larger groups of single-bit storage elements within a two-dimensional nanoscale memory can be accessed in a single operation.
FIG. 1 provides a simple, schematic illustration of an exemplary nanowire crossbar. Although individual nanowires in FIG. 1 are shown with rectangular cross sections, nanowires can also have circular, ellipsoid, or more complex cross sections, and nanowires may have many different widths or diameters and aspect ratios or eccentricities. Nanowires can be fabricated using imprint lithography, by chemical self-assembly on surfaces and transfer to substrates, by chemical synthesis in place, and by a variety of other techniques from metallic and/or semiconducting elements or compounds, doped organic polymers, composite materials, nanotubes and doped nanotubes, and from many additional types of conductive and semiconducting materials. The bistable bit-storage layer 104 is shown in FIG. 1 as a continuous layer between two sets of parallel nanowires, but may alternatively be discontinuous, or may constitute sheath-like molecular coatings around, or component atoms or molecules within, the nanowires, rather than a separate layer. The bistable bit-storage layer 104 may also be composed of a wide variety of different metallic, semiconducting, doped polymeric, and composite materials.
Significant problems may be encountered with respect to interconnection of individual nanowire leads of a nanowire crossbar to submicroscale and microscale signal lines in order to incorporate the nanowire crossbar into conventional electronic devices, including identifying and manipulating individual nanowires. One solution to these problems is to employ demultiplexers with microscale or submicroscale address lines that are integrated with nanowire crossbars. FIG. 2 shows a nanowire-crossbar memory integrated with nanoscale/microscale demultiplexers to allow individual bit-storage elements of the nanowire-crossbar memory to be uniquely accessed via microscale or submicroscale address lines. In FIG. 2, a 16×16 nanowire crossbar 202 has parallel-nanowire layers in which nanowires are extended past the boundaries of the nanowire-crossbar array 202 to form a first demultiplexer 204 and a second demultiplexer 206. Demultiplexer 204 comprises the extended nanowires from a first parallel-nanowire layer of the nanowire crossbar, such as nanowire 208, overlain or underlain by a perpendicular, microscale or submicroscale source-voltage line 210 and four pairs 212-215 of perpendicular microscale or sub-microscale address lines. The second demultiplexer 206 is similarly implemented from the extended nanowires of the second parallel-nanowire layer of the nanowire crossbar. In certain types of implementations, such as the implementation shown in FIG. 2, address lines occur as complementary pairs, each pair representing one bit, and its inverse, of a multi-bit address, while in other implementations, single address lines may be used. Four-bit address input through the four pairs of address lines 212-215 are sufficient to provide a unique address for each of the 16 nanowires, such as nanowire 208, and two four-bit addresses input simultaneously to the four pairs of address lines of each of the two demultiplexers 204 and 206 can uniquely address a particular nanowire junction from among the 256 nanowire junctions within the nanoscale-crossbar array 202.
By placing a WRITE signal on the nanowires of a nanowire-crossbar memory that intersect at a particular single-bit storage element, the state of the single-bit storage element can be set to a desired one of the two bistable states that encode binary digit values “0” and “1.” However, determining the state at a given single-bit storage element by applying a READ signal may be significantly more difficult. Designers, manufacturers, vendors, and integrators of nanowire-crossbar memories, as well as, ultimately, users of such devices have recognized the need for a reliable and efficiently manufactured means for reading the states of single-bit storage elements within a nanowire-crossbar memory, and designers, manufacturers, vendors, integrators, and users of other types of nanowire-crossbar-implemented devices have recognized the need for a reliable and efficiently manufactured interface for interconnecting the nanowire-crossbar-implemented devices with sub-microscale and microscale electronics.